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19-3564; Rev 0; 1/05
KIT ATION EVALU ABLE AVAIL
PMIC for Microprocessors or DSPs in Portable Equipment
General Description Features
Three Regulators and a Reset in One Package High-Efficiency Step-Down Converter Up to 4MHz Fixed Switching Frequency 500mA Guaranteed Output Current 0.6V to 3.3V Adjustable Output Voltage 2% Initial Accuracy Fast Voltage-Positioning Transient Response Internal Synchronous Rectifier Two 300mA LDO Regulators 200mV Dropout at 200mA Load Low 45VRMS Output Noise 3% Accuracy over Line, Load, and Temperature Overcurrent Protection Nine Pin-Selectable Output-Voltage Settings 30ms (min) RESET Output Flag 2.7V to 5.5V Input 115A (typ) Supply Current at No Load Thermal-Overload Protection Tiny 3mm x 3mm x 0.8mm TDFN Package
MAX8620Y
The MAX8620Y micro-power-management integrated circuit (PMIC) powers low-voltage microprocessors or DSPs in portable devices. The PMIC includes a highefficiency step-down DC-DC converter, two lowdropout linear regulators (LDOs), a microprocessor reset output, and power-on/off control logic. This device maintains high efficiency at light loads with a low 115A supply current, and its miniature TDFN package makes it ideal for portable devices. The MAX8620Y's step-down DC-DC converter utilizes a proprietary 4MHz hysteretic-PWM control scheme that allows for ultra-small external components. Internal synchronous rectification improves efficiency and eliminates the external Schottky diode that is required in conventional step-down converters. The output voltage is adjustable from 0.6V to 3.3V, with guaranteed output current up to 500mA. The MAX8620Y's two LDOs offer low 45VRMS output noise and a low dropout of only 200mV at 200mA. Each LDO delivers at least 300mA of continuous output current. The output voltages are pin selectable from 1.8V to 3.3V for flexibility. A microprocessor reset output (RESET) monitors OUT1 and warns the system of impending power loss allowing safe shutdown. RESET asserts during power-up, power-down, shutdown, and fault conditions where VOUT1 is below its regulation voltage.
Ordering Information
PART MAX8620YETD TEMP RANGE -40C to +85C PINPACKAGE 14 TDFN-EP (T1433-2) TOP MARK AAB
Applications
Cellular Handsets Smart Phones/PDA Phones PDAs Wireless LAN Microprocessor and DSP Solutions including MSMTM, XScaleTM, ARMTM, and OMAPTM
VIN
Typical Operating Circuit
IN2 IN1 OUT2 OUT1 1.80V, 2.60V, 2.80V, 2.85V, 3.00V, OR 3.30V* 300mA 1.80V, 2.50V, 2.60V, 2.85V, OR 3.00V* 300mA VLOGIC 100k EN2 HF_PWR PWR_ON RESET LX RESET OUT3 0.6V TO 3.3V 500mA
MAX8620Y
BP
Pin Configuration appears at end of data sheet. MSM is a trademark of QUALCOMM, Inc. XScale is a trademark of Intel Corp. ARM is a trademark of ARM Limited. OMAP is a trademark of Texas Instruments, Inc.
SEL1 SEL2 GND
FB
*USE SEL1 AND SEL2 TO SET VOUT1 AND VOUT2
________________________________________________________________ Maxim Integrated Products
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
ABSOLUTE MAXIMUM RATINGS
IN1, IN2, PWR_ON, RESET, EN2, SEL1, SEL2, HF_PWR, FB, BP to GND ..................................-0.3V to +6.0V OUT1, OUT2 to GND .................................-0.3V to (VIN1 + 0.3V) LX Current ......................................................................1.5ARMS Continuous Power Dissipation (TA = +70C) 14-Pin TDFN (derate 18.2mW/C above +70C) .......1454mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN1 = VIN2 = +3.7V, CIN = 10F, CBP = 0.01F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Supply Voltage Range Shutdown Supply Current SYMBOL VIN1 ISHDN VIN1 = VIN2 = 4.2V, PWR_ON = HF_PWR = GND All outputs enabled, no load Supply Current UNDERVOLTAGE LOCKOUT UVLO Threshold THERMAL PROTECTION Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis REFERENCE (BP) Reference Bypass Output Voltage PWR_ON, HF_PWR, EN2 Input Low Voltage PWR_ON, HF_PWR, EN2 Input High Voltage Input Bias Current HF_PWR Timer LINEAR REGULATORS (OUT1, OUT2) OUT1, OUT2 Output-Voltage Accuracy OUT1, OUT2 Output Current OUT1, OUT2 Output Current Limit OUT1, OUT2 Dropout Voltage VOUT1, VOUT2 IOUT_ ILIM_ VDO VOUT_ = 0V ILOAD = 200mA, TA = +85C (Note 3) ILOAD = 1mA, 3.7V VIN 5.5V 1mA ILOAD 300mA ILOAD = 150mA 300 310 550 200 940 380 0C to +85C -40C to +85C -1.3 -1.5 -1.2 0 mA mA mV +1.8 +1.8 % VBP 0 IBP 1A 1.231 1.250 1.269 V Temperature rising +160 15 C C VUVLO VIN1 = VIN2 rising VIN1 = VIN2 falling 2.70 2.85 2.35 3.05 V IIN1 + IIN2 VOUT1 = VOUT3 = 1.8V, IOUT1 = IOUT3 = 500A, OUT2 disabled CONDITIONS MIN 2.7 5.5 115 430 TYP MAX 5.5 10 140 A UNITS V A
LOGIC AND CONTROL INPUTS (PWR_ON, HF_PWR, EN2) VIL VIH IINB tHF VIN1 = VIN2 = 2.7V to 4.2V (Note 2) VIN1 = VIN2 = 2.7V to 4.2V (Note 2) VPWR_ON = VHF_PWR = VEN2 = 0V or 5.5V From the rising edge of HF_PWR until the one-shot timer expires (Figure 4) 1.44 -1 1.05 1.31 +1 1.46 0.4 V V A s
2
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PMIC for Microprocessors or DSPs in Portable Equipment
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = +3.7V, CIN = 10F, CBP = 0.01F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER OUT1, OUT2 Power-Supply Rejection Ratio SYMBOL CONDITIONS f = 10Hz to 10kHz, COUT_ = 4.7F, ILOAD_ = 30mA f = 100Hz to 100kHz, COUT_ = 4.7F, ILOAD_ = 30mA f = 100Hz to 100kHz, COUT_ = 4.7F, ILOAD_ = 30mA, CBP open STEP-DOWN CONVERTER (OUT3) Output Voltage Range FB Threshold Voltage FB Threshold Line Regulation FB Threshold Voltage Accuracy (Falling) (% of VTH) FB Threshold Voltage Hysteresis (% of VTH) FB Bias Current Current Limit On-Resistance Rectifier-Off Current Threshold Minimum On- and Off-Times VHYS IFB ILIM3P ILIM3N RONP RONN ILXOFF tON tOFF VOL ISINK = 500A VRESET = 5.5V VTHR tRP Percent of the OUT1 regulation voltage (Note 4) Figure 4 84 30 87 60 1 VIN_ - 0.2V VIN1 = VIN2 = 4.2V, VSEL1 = 0V or VIN1, VSEL2 = 0V or VIN1 0.1 OUT3 disabled VFB = 0.5V pFET switch nFET rectifier pFET switch, ILX = -200mA nFET rectifier, ILX = +200mA 675 875 VOUT3 VTH VFB falling VIN1 = VIN2 = 2.7V to 5.5V (Note 2) IOUT3 = 0mA TA = +25C TA = -40C to +85C -2 -3 2 10 10 950 1000 0.65 0.35 30 107 95 0.3 100 90 1200 1200 1.5 0.8 60 0.6 0.6 0.08 +2 +3 3.3 V V %/V % % A mA mA ns MIN TYP 60 45 VRMS 100 MAX UNITS dB
MAX8620Y
Output Noise Voltage
OPEN-DRAIN, ACTIVE-LOW RESET OUTPUT (RESET) RESET Output-Voltage Low RESET Output Leakage Current RESET Threshold Voltage RESET Timeout Period SEL_ Input Low Threshold SEL_ Input High Threshold SEL_ Input Bias Current V nA % ms V V A
LDO OUTPUT-VOLTAGE SELECT INPUTS (SEL1, SEL2)
Note 1: Specifications are 100% production tested at TA = +25C. Maximum and minimum limits over temperature are guaranteed by design and characterization. Note 2: After startup. Note 3: Guaranteed by design. Note 4: RESET asserts low when VOUT1 drops below the specified percent of the OUT1 regulation voltage.
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Typical Operating Characteristics
(VIN1 = VIN2 = 3.7V, PWR_ON = IN1, L = 2.2H (LQH31CN2R2M53), CFF = 150pF, VOUT1 = VOUT2 = 2.6V, VOUT3 = 1.867V (R1 = 150k, R2 = 75k), CIN = 10F, CBP = 0.01F, COUT1 = COUT2 = 4.7F, COUT3 = 2.2F, RESET pulled up with 100k to OUT1, TA = +25C, unless otherwise noted.) INPUT QUIESCENT CURRENT EFFICIENCY vs. LOAD CURRENT vs. INPUT VOLTAGE
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 100 1000 LOAD CURRENT (mA) L = 2.2H L = 1.0H L = 4.7H
MAX8620Y toc01
160 QUIESCENT CURRENT (A) 140 120 100 80 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
INPUT VOLTAGE (V)
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX8620Y toc03
EFFICIENCY vs. OUTPUT VOLTAGE
95 90 EFFICIENCY (%) 85 80 75 70 65 L = 2.2H L = 1.0H
MAX8620Y toc04 MAX8620Y toc06
10 L = 1.0H SWITCHING FREQUENCY (MHz)
100 L = 4.7H
1
L = 4.7H
L = 2.2H
0.1 0 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT (mA)
60 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 OUTPUT VOLTAGE (V)
LIGHT-LOAD SWITCHING WAVEFORMS
MAX8620Y toc05
HEAVY-LOAD SWITCHING WAVEFORMS
VLX 2V/div
VLX 2V/div
VOUT AC-COUPLED
20mV/div
VOUT AC-COUPLED IL
MAX8620Y toc02
100
180
20mV/div 200mA/div
IL 100mA/div
200ns/div
200ns/div
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PMIC for Microprocessors or DSPs in Portable Equipment
Typical Operating Characteristics (continued)
(VIN1 = VIN2 = 3.7V, PWR_ON = IN1, L = 2.2H (LQH31CN2R2M53), CFF = 150pF, VOUT1 = VOUT2 = 2.6V, VOUT3 = 1.867V (R1 = 150k, R2 = 75k), CIN = 10F, CBP = 0.01F, COUT1 = COUT2 = 4.7F, COUT3 = 2.2F, RESET pulled up with 100k to OUT1, TA = +25C, unless otherwise noted.) LOAD TRANSIENT (50mA TO 300mA)
MAX8620Y toc07
MAX8620Y
POWER-UP WAVEFORMS
MAX8620Y toc08
VOUT3 AC-COUPLED
2V/div 50mV/div VIN 200mA/div VOUT3 1V/div 1V/div
IL 300mA 200mA/div 50mA VOUT1 1V/div
ILOAD
VOUT2 2s/div 40s/div
PWR_ON STARTUP/SHUTDOWN WAVEFORMS
MAX8620Y toc09
RESET WAVEFORMS
MAX8620Y toc10
VPWR_ON
2V/div
2V/div
VPWR_ON VOUT3 1V/div VRESET VOUT1 1V/div VOUT1 VOUT2 100s/div 1V/div 10ms/div
1V/div
1V/div
OUT2 SHUTDOWN WAVEFORMS
MAX8620Y toc11
HF_PWR STARTUP WAVEFORMS
MAX8620Y toc12
2V/div VHF_PWR VEN2 1V/div 1V/div
VOUT1 1V/div 1V/div VOUT2 VRESET 200s/div 10ms/div
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Typical Operating Characteristics (continued)
(VIN1 = VIN2 = 3.7V, PWR_ON = IN1, L = 2.2H (LQH31CN2R2M53), CFF = 150pF, VOUT1 = VOUT2 = 2.6V, VOUT3 = 1.867V (R1 = 150k, R2 = 75k), CIN = 10F, CBP = 0.01F, COUT1 = COUT2 = 4.7F, COUT3 = 2.2F, RESET pulled up with 100k to OUT1, TA = +25C, unless otherwise noted.)
OUT1/OUT2 VOLTAGE vs. INPUT VOLTAGE
MAX8620Y toc13
DROPOUT VOLTAGE vs. LOAD CURRENT
350 DROPOUT VOLTAGE (mV) 300 250 200 150 100 50 0 VOUT_ = 3V
MAX8620Y toc14
2.80 2.75 2.70 OUTPUT VOLTAGE (V) 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 3.0 3.5 4.0 4.5 5.0 ILOAD = 300mA ILOAD = 0mA
400
5.5
0
50
100
150
200
250
300
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
OUT1/OUT2 LOAD REGULATION vs. LOAD CURRENT
MAX8620Y toc15
OUT1/OUT2 POWER-SUPPLY RIPPLE REJECTION vs. FREQUENCY
POWER-SUPPLY RIPPLE REJECTION (dB) 70 60 50 40 30 20 10 0 0.1 1 10 FREQUENCY (kHz) 100 1000
MAX8620Y toc16
-0.1 -0.3 LOAD REGULATION (%) -0.5 -0.7 -0.9 -1.1 -1.3 -1.5 0 50 100 150 200 250
80
300
LOAD CURRENT (mA)
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PMIC for Microprocessors or DSPs in Portable Equipment
Pin Description
PIN 1 2 NAME SEL1 SEL2 FUNCTION LDO Output-Voltage Select Input 1. SEL1 and SEL2 set the OUT1 and OUT2 voltages to one of nine combinations (Table 1). LDO Output-Voltage Select Input 2. SEL1 and SEL2 set the OUT1 and OUT2 voltages to one of nine combinations (Table 1). OUT2 Enable Input. Drive EN2 low to enable OUT2. Drive EN2 high to disable OUT2. If the MAX8620Y is placed into shutdown (PWR_ON = HF_PWR = low), OUT2 does not power regardless of the status of EN2 (Table 2, Figure 4). Open-Drain, Active-Low Reset Output. RESET asserts low when VOUT1 drops below 87% (typ) of regulation. RESET remains asserted for tRP after VOUT1 rises above 87% (typ) of regulation. RESET also asserts when OUT1 is disabled (Figure 4). RESET deasserts if OUT1 is enabled and VOUT1 is above 87% of regulation after tRP. Reference Bypass Capacitor Node. Bypass BP with a 0.01F capacitor to GND. BP is high impedance when the MAX8620Y is disabled (PWR_ON = HF_PWR = low). Hands-Free Enable Input. Drive HF_PWR high or apply a pulse to enable the MAX8620Y. Power is enabled for 1.31s (typ) following a rising edge at HF_PWR (Table 2, Figure 4). Power-Enable Input. Drive PWR_ON high to enable the MAX8620Y (Table 2, Figure 4). Drive PWR_ON low to enter shutdown mode. In shutdown, the LX node is high impedance and both LDOs are disabled (depending on the state of HF_PWR). Step-Down Converter Output-Voltage Feedback Input. VFB regulates to 0.6V (typ). Connect FB to the center of an external resistor-divider between LX and GND to set VOUT3 between 0.6V and 3.3V (see the Setting the Step-Down Output Voltage (OUT3) section). Ground. Connect GND to the exposed pad. Inductor Connection. LX is internally connected to the drain of the internal p-channel power MOSFET and the drain of the n-channel synchronous rectifier. LX is high impedance when OUT3 is disabled. Power Input 2. Connect IN2 to IN1 as close to the device as possible. Power Input 1. Connect IN1 to IN2 as close to the device as possible. Bypass IN1 to GND with a 10F ceramic capacitor, as close to the device as possible. 300mA LDO Output 1. Bypass OUT1 to GND with a 4.7F ceramic capacitor for 300mA applications, or a 2.2F ceramic capacitor for 150mA applications. OUT1 is high impedance when disabled. 300mA LDO Output 2. Bypass OUT2 to GND with a 4.7F ceramic capacitor for 300mA applications, or a 2.2F ceramic capacitor for 150mA applications. OUT2 is high impedance when disabled. Exposed Pad. Connect EP to GND.
MAX8620Y
3
EN2
4
RESET
5 6
BP HF_PWR
7
PWR_ON
8 9 10 11 12 13 14 EP
FB GND LX IN2 IN1 OUT1 OUT2 EP
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Detailed Description
The MAX8620Y PMIC is designed to power low-corevoltage microprocessors or DSPs in portable devices. The PMIC contains a fixed-frequency, high-efficiency step-down converter; two low-dropout regulators (LDOs); a 30ms (min) reset timer; and power-on/off control logic (Figure 1). fixed frequency up to 4MHz, allowing for ultra-small external components. The step-down converter output current is guaranteed up to 500mA. When the step-down converter output voltage falls below the regulation threshold, the error comparator begins a switching cycle by turning the high-side pFET switch on. This switch remains on until the minimum ontime (tON) expires and the output voltage is in regulation or the current-limit threshold (ILIM3P) is exceeded. Once off, the high-side switch remains off until the minimum off-time (t OFF) expires and the output voltage again falls below the regulation threshold. During this off period, the low-side synchronous rectifier turns on and remains on until either the high-side switch turns on or the inductor current reduces to the rectifier-off current threshold (ILXOFF = 30mA (typ)). The internal synchronous rectifier eliminates the need for an external Schottky diode.
VIN IN1 pFET IN2 CIN
Step-Down DC-DC Control Scheme
The MAX8620Y step-down converter is optimized for high-efficiency voltage conversion over a wide load range while maintaining excellent transient response, minimizing external component size, and minimizing output voltage ripple. The DC-DC converter (OUT3) also features an optimized on-resistance internal MOSFET switch and synchronous rectifier to maximize efficiency. The MAX8620Y utilizes a proprietary hysteretic-PWM control scheme that switches with nearly
MAX8620Y
STEP-DOWN CONVERTER CONTROL
LX nFET R1
L
OUT3
COUT3 CFF
PWR_ON
CONTROL LOGIC ENABLE UVLO
0.6V FB OUT1 LDO1 CONTROL
R2
OUT1 COUT1
HF_PWR ONESHOT TIMER SEL1 SEL2 OUTPUTVOLTAGE SELECT IN1
RPU RESET
RESET
RESET
OUT2 LDO2 CONTROL EN2 COUT2 EN2
OUT2
BP REFERENCE CBP GND GND
Figure 1. Functional Diagram 8 _______________________________________________________________________________________
PMIC for Microprocessors or DSPs in Portable Equipment
Voltage-Positioning Load Regulation
As seen in Figure 2, the MAX8620Y uses a unique stepdown converter feedback network. By taking feedback from the LX node through R1, the usual phase lag due to the output capacitor is removed, making the loop exceedingly stable and allowing the use of a very small ceramic output capacitor. This configuration causes the output voltage to shift by the inductor series resistance multiplied by the load current. This output-voltage shift is known as voltage-positioning load regulation. Voltage-positioning load regulation greatly reduces overshoot during load transients, which effectively halves the peak-to-peak output-voltage excursions compared to traditional step-down converters. See the Load-Transient Response graph in the Typical Operating Characteristics section. Two low-dropout, low-quiescent-current, high-accuracy linear regulators supply loads up to 300mA each. The LDO output voltages are set using SEL1 and SEL2 (see Table 1). As shown in Figure 3, the LDOs include an internal reference, error amplifiers, p-channel pass transistors, internal-programmable voltage-dividers, and an OUT1 power-good comparator. Each error amplifier compares the reference voltage to a feedback voltage and amplifies the difference. If the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled lower, allowing more current to pass to the outputs and increasing the output voltage. If the feedback voltage is too high, the pass-transistor gate is pulled up, allowing less current to pass to the output.
MAX8620Y
Table 1. MAX8620Y Output-Voltage Selection
SEL1 IN1 IN1 IN1 OPEN OPEN OPEN GND GND GND SEL2 IN1 OPEN GND IN1 OPEN GND IN1 OPEN GND OUT1 3.00V 2.85V 3.00V 3.30V 2.80V 3.30V 2.85V 2.60V 1.80V OUT2 2.50V 2.85V 3.00V 2.50V 2.60V 1.80V 2.60V 2.60V 2.60V
IN2
OUT1 COUT1 4.7F 100k
2.6V 300mA
I/O
Li+ CELL
CIN 10F
IN1 RESET L 2.2H OUT3, 500mA COUT3 2.2F DSP OR P 2.6V 300mA COUT2 4.7F RESET IN
MAX8620Y
BP CBP 0.01F
LX R1 150k FB CFF 150pF
CORE
SEL2 SEL1 OUT2 POWER-ON KEY VBATT 1M GND HF_PWR EN2 PWR_ON
R2 75k
ANALOG
ON/OFF
Figure 2. Typical MAX8620Y DSP or P Application
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
IN1
MAX8620Y MOS DRIVER WITH ILIMIT PWR_ON ERRORAMP 2 OUT2 P
HF_PWR
ON/OFF LOGIC
P
ERRORAMP 1 EN2
MOS DRIVER WITH ILIMIT
OUT1
LDO THERMAL SENSOR BP GND
1.25V REF 87% REGULATION POK TIMER
RESET
Figure 3. Linear-Regulator Functional Diagram
LDO Output-Voltage Selection (SEL1, SEL2)
As shown in Table 1, the LDO output voltages, OUT1 and OUT2, are set according to the logic states of SEL1 and SEL2. SEL1 and SEL2 are trilevel inputs: IN1, open, and GND. The input voltage, VIN1, must be a dropout voltage (VDO) greater than the selected OUT1 and OUT2 voltages.
PWR_ON is high (Table 2). OUT1, OUT2, and OUT3 are all disabled when PWR_ON is low. HF_PWR can temporarily bring the MAX8620 out of power-down mode when PWR_ON is low (see the HF_PWR section). In power-down, the control circuitry, internal-switching pchannel MOSFET, and the internal synchronous rectifier (n-channel MOSFET) turn off, and LX becomes high impedance. In addition, both LDOs are disabled.
Power-Enable Input (PWR_ON)
Drive PWR_ON low to place the MAX8620Y in powerdown mode and reduce supply current to 5.5A (typ). Connect PWR_ON to IN1 = IN2 or logic-high to enable the MAX8620Y. EN2 enables and disables OUT2 when
OUT2 Enable (EN2)
Drive EN2 low to enable OUT2. Drive EN2 high to disable OUT2. If the MAX8620Y is placed into powerdown using PWR_ON (PWR_ON = low), OUT2 does not power regardless of the status of EN2 (Table 2).
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Table 2. MAX8620Y Power Modes
PWR_ON 1 1 0 0 0 HF_PWR* X X 1 1 0 EN2 1 0 1 0 X OUT1 AND OUT3 Enabled Enabled Enabled Enabled Disabled OUT2 Disabled Enabled Disabled Enabled Disabled
*A rising edge at HF_PWR initiates a 1.31s one-shot timer. The status of HF_PWR shown in Table 2 indicates whether the one-shot period has expired as follows: 1 = During tHP 0 = tHP has expired
Hands-Free Enable Input (HF_PWR)
A rising edge at HF_PWR generates an internal oneshot pulse that enables the MAX8620Y for 1.31s (tHF). If HF_PWR remains high after tHF expires, the MAX8620Y reenters shutdown. During tHF, OUT3 and OUT1 are enabled so the microprocessor (P) can initialize and assert a logic-high at PWR_ON. OUT2 enables during tHF if EN2 is low. Once PWR_ON is high, the status of HF_PWR is ignored. If PWR_ON remains low after tHF expires, the MAX8620Y reenters shutdown.
Power-Supply Sequencing
The step-down converter output (OUT3) always powers up first and powers down last (Figure 4). OUT1 powers approximately 70s after OUT3, and OUT2 powers approximately 50s after VOUT1 reaches 87% (typ) of its regulation voltage. When PWR_ON goes low, OUT1 turns off, then OUT2 turns off, then OUT3 turns off 50s after PWR_ON goes low.
50s HF_PWR tHF PWR_ON
OUT3
tSU1 VTHR
OUT1 tSU2
OUT2
RESET tRP
EN2
Figure 4. MAX8620Y Power-Supply Sequencing
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Reset Output (RESET)
RESET is an open-drain, active-low output that indicates the status of OUT1. RESET is typically pulled up through a 100k resistor to the system logic voltage. RESET asserts at power-up. The reset timer begins once V OUT1 reaches 87% of regulation. RESET deasserts 60ms after VOUT1 rises above 87% (typ) of regulation (see the Typical Operating Characteristics). RESET also asserts when OUT1 is disabled. event of fault conditions. For continuous operation, do not exceed the absolute-maximum junction-temperature rating of TJ = +150C.
Applications Information
Power-On Closed-Loop System
When the MAX8620Y is used in conjunction with a microcontroller, HF_PWR and PWR_ON can implement a short-key power-on closed-loop system (Figure 5). The MAX8620Y detects a rising edge at HF_PWR and generates an internal 1.31s (typ) one-shot pulse that begins power sequencing and temporarily enables OUT1, OUT2, and OUT3 (depending on the state of EN2). The 1.31s of power provides time for the processor to initialize and assert a logic-high at PWR_ON. Once PWR_ON is driven high, OUT3, OUT1, and OUT2 (depending on the state of EN2) remain enabled. If the microcontroller does not drive PWR_ON high during tHF, the MAX8620Y disables OUT1, OUT2, and OUT3, and reenters shutdown.
Reference Bypass Capacitor Node (BP)
An optional 0.01F bypass capacitor at BP creates a lowpass filter for LDO noise reduction. OUT1 and OUT2 exhibit 45VRMS of output-voltage noise with CBP = 0.01F and COUT1 = COUT2 = 4.7F.
Undervoltage Lockout
VIN1 = VIN2 must exceed the 2.85V typical undervoltage-lockout threshold (VUVLO) before the MAX8620Y enables OUT3 to begin power-supply sequencing (see the Power-Supply Sequencing section). The UVLO threshold hysteresis is typically 0.5V.
Current Limiting
The MAX8620Y 300mA LDOs limit their output current to ILIM_ = 550mA (typ). If the LDO output current exceeds ILIM_, the corresponding LDO output voltage drops. The step-down converter limits ILIM3P to 675mA (min).
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8620Y. Independent thermal-protection circuits monitor the step-down converter and the linearregulator circuits. When the MAX8620Y junction temperature exceeds T J = +160C, the thermal-overload protection circuit disables the corresponding circuitry, allowing the IC to cool. The thermal-overload protection circuitry enables the MAX8620Y after the junction temperature cools by 15C, resulting in a pulsed output during continuous thermal-overload conditions. Thermaloverload protection safeguards the MAX8620Y in the
POWER-ON KEY
MAX8620Y
HF_PWR PWR_ON
VCORE VI/O VANA
P
1M
PWR HOLD
POWER-HOLD SIGNAL
Figure 5. Short-Key Power-On Closed-Loop System
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PMIC for Microprocessors or DSPs in Portable Equipment
If a long-key press is preferred, see Figure 6. PWR_ON must remain high until a microprocessor asserts a logichigh signal when using this circuit. If a system includes multiple power-on sources, use a diode OR configuration, as shown in Figure 7. current, IFB, is typically 10nA. Select R2 so the resistordivider bias current dominates IFB by a factor of 10. A wide range of resistor values is acceptable, but a good starting point is to choose R2 = 100k. R1 is given by: V R1 = R2 OUT3 - 1 VFB where VFB = 0.6V. VOUT3 can be set between 0.6V and 3.3V, but the stepdown converter dropout voltage and inductor voltage drop impact how close VOUT3 can be to VIN2. Total dropout voltage is a function of the pFET on-resistance, the DCR of the inductor, and the load as follows: VOUT3(DO) = IOUT3 x (RONP + DCRINDUCTOR ) For example, with 300mA load:
POWER-HOLD SIGNAL
MAX8620Y
POWER-ON KEY
MAX8620Y
PWR_ON
VCORE VI/O VANA
P
PWR HOLD 1M
VOUT3(DO) = 300mA x (0.65 + 50m) = 210mV As a result, V IN1 = V IN2 must exceed the desired VOUT3 by 210mV to maintain regulation.
Figure 6. Long-Key Power-On Closed Loop
Inductor Selection
The MAX8620Y step-down converter operates with inductors between 1H and 4.7H. Low inductance values are physically smaller but require faster switching, which results in some efficiency loss. See the Typical Operating Characteristics section for efficiency and switching frequency versus inductor value plots. The inductor's DC current rating needs to be only 100mA greater than the application's maximum load current because the MAX8620Y step-down converter features zero-current overshoot during startup and load transients. For output voltages above 2.0V, when light-load efficiency is important, the minimum recommended inductor is 2.2H. For optimum voltage-positioning load transients, choose an inductor with DC series resistance in the 50m to 150m range (Table 3). For higher efficiency at heavy loads (above 200mA) or minimal load regulation (but some transient overshoot), the resistance should be kept below 100m. For light-load applications up to 200mA, much higher resistance is acceptable with very little impact on performance.
AC ADAPTER HANDS-FREE KIT
MAX8620Y
HF_PWR PWR_ON
VCORE VI/O VANA
P
PWR HOLD
POWER-ON KEY
1M
POWER-HOLD SIGNAL
Figure 7. Multiple Power-On Inputs
Setting the Step-Down Output Voltage (OUT3)
Select a step-down converter output voltage between 0.6V and 3.3V by connecting a resistor voltage-divider between LX, FB, and GND (see Figure 2). The FB bias
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Table 3. Suggested Inductors
MANUFACTURER SERIES LB2012 INDUCTANCE (H) 1.0 2.2 1.0 1.5 2.2 3.3 1.0 1.5 2.2 3.3 1.0 1.5 2.2 3.3 4.7 2.2 4.7 2.2 4.7 2.2 4.7 1.0 2.2 4.7 2.2 4.7 1.5 2.2 3.3 1.5 2.2 2.7 3.3 1.5 2.2 3.3 4.7 ESR () 0.15 0.23 0.09 0.11 0.13 0.20 0.06 0.07 0.09 0.11 0.08 0.11 0.13 0.16 0.20 0.23 0.40 0.13 0.25 0.09 0.13 0.06 0.10 0.15 0.10 0.17 0.13 0.17 0.19 0.10 0.12 0.15 0.17 0.05 0.08 0.10 0.14 CURRENT RATING (mA) 300 240 455 350 315 280 500 400 340 270 775 660 600 500 430 410 300 510 340 510 340 1000 790 650 400 300 1230 1080 1010 1290 1140 980 900 900 780 600 500 DIMENSIONS (mm) 2.0 x 1.25 x 1.25 = 3.1mm3 2.0 x 1.6 x 1.8 = 5.8mm3
LB2016
LB2518
2.5 x 1.8 x 2.0 = 9mm3
Taiyo Yuden LBC2518
2.5 x 1.8 x 2.0 = 9mm3
CB2012 CB2016 CB2518
2.0 x 1.25 x 1.25 = 3.1mm3 2.0 x 1.6 x 1.8 = 5.8mm3 2.5 x 1.8 x 2.0 = 9mm3 3.2 x 2.5 x 1.7 = 14mm3 4.5 x 3.2 x 0.9 = 13mm3 3.6 x 3.6 x 1.0 = 13mm3
LQH32C_53 Murata LQM43FN
D310F TOKO D312C
3.6 x 3.6 x 1.2 = 16mm3
Sumida
CDRH2D11
3.2 x 3.2 x 1.2 = 12mm3
14
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PMIC for Microprocessors or DSPs in Portable Equipment
Capacitor Selection
Step-Down Converter Output Capacitor The output capacitor, COUT3, is required to keep the output voltage ripple small and to ensure regulation loop stability. COUT3 must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. Due to the unique feedback network, the output capacitance can be very low. For most applications, a 2.2F capacitor is sufficient. For optimum load-transient performance and very low output ripple, the output capacitor value in Fs should be equal to or larger than the inductor value in Hs. Input Capacitor The input capacitor, CIN, reduces the current peaks drawn from the battery or input power source and reduces switching noise in the IC. The impedance of CIN at the switching frequency should be kept very low. Ceramic capacitors with X5R or X7R dielectrics are highly recommended due to their small size, low ESR, and small temperature coefficients. Use a 10F ceramic capacitor or equivalent amount of multiple capacitors in parallel between IN1 and GND. Connect C IN as close as possible to the MAX8620Y to minimize the impact of PC board trace inductance. Feed-Forward Capacitor The feed-forward capacitor, CFF, sets the feedback loop response, controls the switching frequency, and is critical in obtaining the best efficiency possible. Choose a small ceramic C0G (NPO) or X7R capacitor with a value given by: CFF = L x 10S R1 lent series resistance (ESR) affects stability and output noise. Use output capacitors with an ESR of 0.1 or less to ensure stability and optimum transient response. Surface-mount ceramic capacitors have very low ESR and are commonly available in values up to 10F. Connect COUT as close as possible to the MAX8620Y to minimize the impact of PC board trace inductance.
MAX8620Y
Power Dissipation and Thermal Considerations
The MAX8620Y total power dissipation, PD, is estimated using the following equations: PD = PLOSS(OUT1) + PLOSS(OUT2) + PLOSS(OUT3) PLOSS(OUT1) = I(OUT1) (VIN PLOSS(OUT3) = PIN(OUT3) 1
-
PLOSS(OUT2) = I(OUT2) (VIN - VOUT2 )
-
VOUT1)
2
100
- I(OUT 3)
x RDC(INDUCTOR) where PIN(OUT3) is the input power for OUT3, is the step-down converter efficiency, and RDC(INDUCTOR) is the inductor's DC resistance. The die junction temperature can be calculated as follows: TJ = TA + PD x JA where JA = 55C/W at +70C. TJ should not exceed +150C in normal operating conditions.
PC Board Layout and Routing
High switching frequencies and relatively large peak currents make the PC board layout a very important aspect of design. Good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Connect CIN close to IN1 and GND. Connect the inductor and output capacitors (COUT3) as close to the IC as possible and keep the traces short, direct, and wide. The traces between COUT3, CFF, and FB are sensitive to inductor magnetic-field interference. Route these traces between ground planes or keep the traces away from the inductor.
where R1 is the resistor between LX and FB (Figure 2). Select the closest standard value to CFF as possible. LDO Output Capacitors For applications that require greater than 150mA of output current, connect a 4.7F ceramic capacitor between the LDO output and GND. For applications that require less than 150mA of output current, connect a 2.2F ceramic capacitor between the LDO output and GND. The LDO output capacitor's (COUT_) equiva-
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Connect GND to the ground plane. The external feedback network should be very close to the FB pin, within 0.2in (5mm). Keep noisy traces, such as the LX node, as short as possible. Connect GND to the exposed paddle directly under the IC. Figure 8 and the MAX8620Y evaluation kit illustrate examples of PC board layout and routing schemes.
Pin Configuration
OUT2 OUT1
TOP VIEW
LX
GND 9 6 HF_PWR
IN1
IN2
14
13
12
11
10
MAX8620Y
OUT2 OUT1
SEL1
SEL2
RESET
U1 C6 R1 L1 C4 R2 C5
GND OUT3
RESET HF_PWR PWR_ON
3mm x 3mm x 0.8mm TDFN
Chip Information
Figure 8. Recommended PC Board Layout
TRANSISTOR COUNT: 4481 PROCESS: BiCMOS
16
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PWR_ON
SEL1 SEL2 EN2
C3 C2
IN C1
1
2
3 EN2
4
5 BP
FB 8 7
PMIC for Microprocessors or DSPs in Portable Equipment
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS
MAX8620Y
D2 D A2
N
PIN 1 ID
0.35x0.35 b
PIN 1 INDEX AREA
E DETAIL A
E2 e
[(N/2)-1] x e REF.
A1
k
C L
C L
A
L e e
L
PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
-DRAWING NOT TO SCALE-
21-0137
G
1
2
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PMIC for Microprocessors or DSPs in Portable Equipment MAX8620Y
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 MAX. 0.80 3.10 3.10 0.05
0.20 0.40 0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T633-2 T833-1 T833-2 T833-3 T1033-1 T1433-1 T1433-2 N 6 6 8 8 8 10 14 14 D2 1.500.10 1.500.10 1.500.10 1.500.10 1.500.10 1.500.10 1.700.10 1.700.10 E2 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.95 BSC 0.65 BSC 0.65 BSC 0.65 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEA MO229 / WEEC MO229 / WEEC MO229 / WEEC MO229 / WEED-3 ------b 0.400.05 0.400.05 0.300.05 0.300.05 0.300.05 0.250.05 0.200.05 0.200.05 [(N/2)-1] x e 1.90 REF 1.90 REF 1.95 REF 1.95 REF 1.95 REF 2.00 REF 2.40 REF 2.40 REF
DOWNBONDS ALLOWED
NO NO NO NO YES NO YES NO
PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
-DRAWING NOT TO SCALE-
21-0137
G
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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